The present invention relates to manufacturing methods of semiconductor devices, and more particularly to a technique effectively applied to a manufacturing technology of a semiconductor device including a MISFET with a metal gate electrode.
A metal insulator semiconductor field effect transistor (MISFET, namely, MIS field-effect transistor, or MIS transistor) can be manufactured by forming a gate insulating film over a semiconductor substrate, forming a gate electrode over the gate insulating film, and forming source and drain regions by ion implantation.
In a complementary MISFET (CMISFET), gate electrodes are formed using materials with different work functions (for polysilicon, Fermi levels) so as to achieve a low threshold voltage in both of an n-channel MISFET and a p-channel MISFET, which is the so-called dual gate technique. That is, n-type impurities and p-type impurities are implanted into polysilicon films forming gate electrodes of the n-channel MISFET and p-channel MISFET. As a result, the work function (Fermi level) of the gate electrode material of the n-channel MISFET is brought close to the conduction band of silicon, and the work function (Fermi level) of the gate electrode material of the p-channel MISFET is brought close to the valence band of silicon, which achieves reduction in threshold voltage.
However, gate insulating films have recently been made thinner together with microfabrication of CMISFET elements. In use of a polysilicon film as a gate electrode, the influence of depletion of the gate electrode has not been negligible. For this reason, a technique is proposed in which a metal gate electrode is used as a gate electrode to suppress the depletion of the gate electrode.
Since the gate insulating film has been made thinner by microfabricating the CMISFET element, when using a thin silicon oxide film as a gate insulating film, electrons flowing through a channel of the MISFET tunnel through a barrier formed of the silicon oxide film to flow into the gate electrode. That is, the so-called tunnel current is generated. Another technique is proposed in which material having a dielectric constant higher than that of a silicon oxide film is used as a gate insulating film thereby to increase the physical thickness of a gate electrode even with the same capacity so as to reduce leak current.
Non-patent documents 1 and 2 disclose techniques regarding a CMOSFET using a metal gate electrode and a high-dielectric-constant gate insulating film.